As systems-on-chip become more pervasive, designers will need to address the question of when to integrate RF functionality on more and more projects. Although there will be many applications integrating digital with RF, a system-on-chip will by definition be predominantly digital. So, SoC designers working on RF systems have to make the decision either to incorporate the RF onto a large, mostly digital SoC or to include it as a separate IC. Suppose you want to build a true "single-chip" Bluetooth radio. You would need to place the RF portion inside the chip, which would eliminate all external SAW, ceramic, inductor and varactor components. What are the trade-offs of implementing RF inside the chip vs. surrounding the mainly digital chip with the needed RF circuits? This article attempts to illustrate them.
Although the range of RF applications that can be considered for SoC devices is varied, the range of technologies is not. Whether they contain RF blocks or not, system chips will be built in mainstream digital CMOS technologies. Given the high digital gate count associated with an SoC, implementing one in a boutique RF process would be cost-prohibitive. Fortunately, the application of CMOS to RF circuits is well-established and foundries offer digital processes that have suitable performance for many RF applications. In some processes, the situation is even better, with the availability of analog options such as MIM caps and resistors, or even RF-specific options such as thick metal for inductors. From an RF designer's perspective, performance will take another step forward if foundries are able to bring silicon germanium into the mainstream as planned.
Support for RF design has improved in the last few years. Major foundries have invested in RF-specific characterization and developed RF-specific models for their processes.
Even though SoC process technologies will support RF, bringing an RF block onto an SoC changes the landscape dramatically. The requirements for RF I/O will influence floor planning as well as package selection. Performance requirements will affect technology selection and may force the inclusion of process options that increase cost. Further, problems arising from noise and spurious signals may make system performance strongly dependent on isolation between the digital and RF blocks. All of these factors complicate both the technical and economic decisions to include RF on an SoC.
The technical trade-off is difficult to quantify but is a function of the degree of digital noise on the IC and the performance required of the RF circuit. The economic trade-off can be dealt with quantitatively as a function of process technology, amount of digital circuitry and amount of RF circuitry.
Technical issues
The technical decision to incorporate an RF block in an SoC is highly dependent on the details of the situation. For integration to be technically feasible, it must be possible to adequately isolate the RF block from the digital section and to meet the RF I/O requirements in a package compatible with the digital I/O requirements.
Although signals from an RF block are unlikely to affect the digital section of an SoC, digital noise coupling into the RF block can be a problem, either reducing the sensitivity of the RF system or introducing spurious signals that are unacceptable in the transmitted out-put. Tolerable coupling levels are system dependent. For example, operation in the 2.4-GHz ISM band requires effectively that wideband spurious signals in the transmitted output be below about -40 dBm.
For a Class 2 or Class 3 Bluetooth transmitter with output power near 0 dBm, this means that the spurious signals must be -40 dBc. Under the plausible assumption that the internal RF transmit signals are on the same order as the digital noise signals, roughly 50 dB of isolation will be required to meet the FCC requirement with some margin for error. This level of isolation is relatively easy to achieve by following standard "best practices" such as differential signal paths, filtered bias lines and substrate shields under inductors and critical signal paths. For a Class 1 Bluetooth system, the transmitted power can be as high as 20 dBm and much better isolation will be required. In fact, the performance requirements of most systems will push the isolation that can be achieved when the RF is on a predominately digital IC. Unfortunately, substrate coupling and other coupling paths are difficult to model. Designers will have to rely on experience and, if necessary, silicon spins.
RF blocks usually require low-inductance access to the outside world for both signal and power supply lines. The high pin count typical of SoC devices means that operation in the various flavors of quad flat packs is likely to be impractical. Ball grid arrays are better and are perhaps the most practical choice for RF systems-on-chip. Fortunately, the increasingly popular option of solder-bump assembly is nearly ideal for RF applications and makes the SoC package environment as good as it is for a standalone RF IC. For a packaged SoC, the RF block will most likely need to be placed at the corner of the die and, unless the RF block is very small, its I/O will occupy a significant fraction of the die periphery, compressing the digital I/O and raising the possibility of assembly issues.
Economic issues
The ongoing evolution of CMOS technology to smaller geometries is highly beneficial to developing large digital SoC devices. This advance comes at the expense of significantly higher cost/mm2 for the silicon. The net cost per gate drops for digital ICs because of the decrease in die size. Unfortunately, the cost goes up for analog and RF blocks because the size remains essentially the same.
A similar situation applies for operating voltage. Reduced voltage helps by reducing power for digital blocks, but it makes analog and RF design significantly more difficult: Dynamic range is reduced, circuit topology choices are more limited and external loads are more difficult to drive. Fortunately, the inherent speed increase that comes with reduced gate length can be used either to operate at higher frequencies or to reduce power consumption at a given frequency, and is beneficial for both RF and digital circuits. Using an 0.18- or 0.13-micron CMOS technology for RF has some benefits over 0.25 micron but is more expensive and in many cases actually makes the RF design more difficult.
The cost impact of including RF will be dependent on the relative amount of digital and analog circuitry on the S0C. Consider a simplified case comparing 0.25-, 0.18- and 0.13-micron technologies. To make a fair comparison, cost per mm2 has been normalized to 0.7, 1 and 1.5 for these three technologies, respectively. If RF is included, the cost is taken to be 20 percent higher to cover process options such as thick metal and MIM caps. Similarly, the relative digital density is taken to be 0.4, 1 and 1.9, respectively.
To generate Fig. 1, an RF silicon area of 10 mm2 was chosen independent of technology, and it was assumed that all ICs are core-limited and that a 350-micron pad ring would be placed around the core. Fig. 1 shows the cost for single- and two-IC solutions in each of these technologies. Note that in all the cases with higher gate counts representative of an SoC, the combined IC solution costs more because the cost premium for RF process options applies to the digital circuitry. Even so, the cost is not significantly different if both ICs are built in the same process.
Fig. 2 shows similar curves for the case where the RF IC is built in the 0.25-micron process and the digital IC is built in each of the three processes. The single-IC curves are also shown for comparison. For systems with high digital content, the cost is significantly lower when the RF IC is built in the 0.25-micron process and the digital IC is built in the 0.13-micron process. Applying the most cost-effective technology to each problem minimizes the overall cost.
This simplified model neglects several factors that could influence the cost trade-off. Perhaps most significant is that the effect of additional I/O required for the two-dice solution has been neglected implicitly, in the assumption that the dice are core-limited and by leaving I/O cost out of the analysis. Neglecting I/O is valid because in many cases, only minimal I/O is required to drive an RF block. In cases with substantial digital bandwidth between the digital and the RF (for example, a digital I/Q interface), I/O cost will skew the decision toward one IC and the SoC designer will have to weigh other factors to make a decision.
In conclusion, various factors might motivate bringing an RF block onto an SoC such as the expectation of lower cost, lower area or higher performance. For predominately digital mixed-signal systems, cost will be higher with RF integrated on the SoC and there are likely to be few cases where the increase in cost and other liabilities associated with a one-IC solution will justify integration. So, the SoC devices with integrated RF will be the small number of systems with unusual requirements, such as an extreme need for minimum size or very high digital bandwidth to the RF block.
For a "single-chip" Bluetooth radio comprising RF, baseband and support circuitry, it is reasonable to take the area of the RF and digital at 10 mm2 each in an 0.18-micron process. Such a system has a normalized digital gate count of 10 (since gate count is normalized to digital area in 0.18 micron) and thus is at the low end of the range considered in Fig. 2. Even so, the figure indicates that a two-chip solution would be somewhat less costly. Because the cost differential is not huge and other factors tend to favor integration, the decision for a basic Bluetooth radio is more or less a toss-up. However, if current technology trends continue, the one-IC solution is likely to become decisively less attractive.
The disincentive to integrate RF on SoC devices is likely to persist for some time because, as system chips move down the CMOS technology road map, bringing RF blocks onto an SoC becomes even less attractive for most applications. This is not to say that RF will not be implemented in advanced CMOS technologies or that there won't be mixed-signal RF ICs. Rather, for the foreseeable future, the combination of RF with digital will be primarily limited to situations where the digital is comparable with or smaller than the RF, and where the digital implements a valuable function most naturally partitioned with the RF.
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Tony Caviglia (tonyc@tality.com) is a senior member of the consulting staff for Tality Corp. (San Jose, Calif.), a Cadence Design Systems subsidiary and an electronic product-development outsourcing provider. He has been involved in RF IC design for more than 10 years, recently working on Bluetooth systems at Tality's Analog/Mixed Signal Design Center in Columbia, Md. Caviglia received his PhD in electronic engineering from the University of Maryland.
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Copyright © 2002 CMP Media LLC
2/1/02, Issue # 14152, page 8.
